Testing an integrated device with an embedded function, such as memory which is built in a chip, may result in various problems as the embedded function may not be directly accessible from outside the chip. Generally, two methods have been utilized to test embedded functions such as memory in an integrated device. One method is to directly approach the control terminals of the memory from the input and output terminals of the device, and the other is to embed in the device a circuit for automatically testing the memory portion of the device. These built-in circuits are often referred to as a built-in self test (BIST) circuit.
The first approach of making the embedded memory accessible through input/output terminals may be undesirable as such terminals occupy terminals which could otherwise be used by the device for other functions. Accordingly, making an embedded memory array externally accessible may be less efficient than testing the array internal to the device. Furthermore, special test equipment may be required to test the embedded memory of the device.
In part as a result of the limitations of making embedded memory externally accessible, built-in self test circuits have been widely used to test memory within the chip. Built-in self test circuits can eliminate the need for additional input and output terminals of the device for testing memory and can be easily realized because of their simple construction. As a result, as the size of the embedded memory increases built-in self test circuits become more practical and useful.
In spite of these advantages, one disadvantage of the built-in self test circuitry is that it may malfunction and thereby indicate an otherwise acceptable device is defective. Accordingly, the built-in self test circuit should be tested before it is relied upon to other functions of the device. The methods for testing built-in self test circuits are similar to those for testing general function modules. For example, if an integrated device utilizes a scan method of testing modules the testing of the built-in self test circuit can be easily performed utilizing known scan test techniques. However, in many instances scan testing is not a viable option for testing a device. In such a case another method for testing the built-in self test circuit of an integrated device should be considered. Accordingly, because of the shortcomings of existing built-in testing techniques, there exists a need for improvements in testing of built-in self test circuitry of integrated devices.